FPGAcademy provides teaching material for a number of courses that are part of a typical Engineering/Computer Science curriculum. For each course we offer tutorials that show you how to use related software tools and hardware boards, a set of laboratory exercises (with solutions available to course instructors), and Alteralectual property such as design examples. Some of the tutorials and laboratory exercises rely on software tools and Alteralectual property from Altera® Corporation. Course instructors and students can obtain access to these Altera products by becoming a member of the Intel FPGA Academic Program.
Several types of courses are available. Select the collapsible menus below to browse the available materials.
This teaching material covers the basic concepts needed to understand and design digital logic circuits—the circuits from which computers, and many other types of products, are built. In computer engineering/science curriculum, digital logic is a key part of an introductory course in computer hardware, typically presented in the second year of the program.
The Digital Logic laboratory exercises are intended to be used with one of the FPGA boards described under Teaching and Project Boards. Each of these boards features an Altera® FPGA and a collection of basic input/output devices (switches, LEDs, and seven-segment displays, and so on) that is useful for demonstrating the functionality of logic circuits. The main software tool used to implement logic circuits in hardware is the Altera® Quartus® CAD system.
If the Digital Logic laboratory exercises are being done without access to an FPGA board, for example in a remote-learning environment, then the laboratory exercises can be done using a simulation-based approach. The main software tools that are used for simulation of logic circuits include the ModelSim and Questa simulators, and the DESim software application, described in Software Tools.
Two sets of tutorials are available to support Digital Logic. One set, Digital Logic Hardware Design provides instructions for implementing logic circuits in Altera® FPGAs using the Altera® Quartus® Prime CAD tools with Verilog or VHDL. The other tutorial set, Digital Logic Simulation and Debug discussses various tools that are available for the simulation of logic circuits with Verilog or VHDL. This latter set of tutorials is especially important if the laboratory experiments are being done in a remote-learning environment, without direct access to FPGA laboratory boards.
These laboratory exercises begin with fundamental concepts and perform simple operations on the DE-series boards, like using switches and controlling LEDs and seven-segment displays. These exercises assume that students are just beginning to learn about digital logic concepts. Subsequent exercises progress to more advanced topics such as arithmetic circuits, flip-flops, counters, state machines, memories, data paths, and simple processors. Instructors of courses may choose to adopt the entire sequence of exercises, only selected exercises, or just parts of some exercises. We have tried to make the material as modular as possible so that instructors can combine these exercises with their own teaching materials.
Each exercise consists of multiple parts. In most cases the solution required for the early parts can be reused in a modular fashion in later parts. Also, the solutions produced for early exercises are often reusable for parts of more advanced exercises. Our basic approach is to encourage students to develop their circuits in small increments and to build larger circuits in a modular, hierarchical fashion.
As an aid for Course Instructors, we provide complete solutions in Verilog and VHDL code for all lab exercises. Password-controlled access to these solutions is provided through the Altera® FPGA Academic Program. To request access, the Course Instructor must be a Member of the Altera FPGA Academic Program and can submit a request for Solutions and Source Files.
| Lab Exercise | Downloads | |
|---|---|---|
| Verilog | VHDL | |
This course introduces key concepts in the design of computer systems, including processors, memory, assembly-language code and C code. This material is typically presented in the second year of a computer engineering/science curriculum. Our material supports two different processors: the Altera® Nios® soft processor, and the ARM* Cortex-A9 processor that is available in some Altera SoC FPGAs.
The Computer Organization laboratory exercises are intended to be used with one of the FPGA boards described under Teaching and Project Boards. Each of these boards features an Altera® FPGA or SoC FPGA, a set of input/output devices (switches, LEDs, seven-segment displays, video output, and so on), memory, and other features that are useful for demonstrating the capabilities of processors. The main software tool used for assembling/compiling software code to be implemented on an FPGA board is the Gnu Project Debugger (GDB) for Nios V and the Monitor Program for other processors. For simulating code, or for working in a remote learning environment, the CPUlator provides a complete development and debugging environment.
For each of our supported laboratory boards (see
Teaching and Project Boards) we have developed
an accompanying Computer System. Each of these Computer Systems includes one
or more processors, memory ports, basic input/output ports (for switches,
lights, etc.), and multimedia ports (for video, audio, and the like).
Computer Systems for Nios V can be obtained as part of the setup files for
using GDB with Nios V (see
Tutorials).
For ARM and Nios II, the computer systems are
provided with the Monitor Program software development environment, which can be
installed via the Software Tools tab.
Our Computer Organization laboratory exercises are
designed for use with these Computer Systems, which are described in detail below.
| Computer System Name | Documentation |
|---|
The tutorials in Computer Organization System Design introduce both the ARM Cortex-A9 and Nios processors, as well as the tools that are available for developing software code for these processors.
The Hardware Components tutorials show you how to use some of the complex input/output devices that are connected to either the ARM or Nios processor.
These laboratory exercises progress through the fundamentals concepts that are taught in Computer Organization courses, including assembly-language code, different types of instructions and addressing modes, memory, stacks, subroutines, interrupts, and C code.
Each exercise consists of multiple parts that build upon one another in a modular fashion. The exercises make use of various input/output devices to perform experiments that are both interesting and pedagogically valuable.
As an aid for Course Instructors, we provide complete solutions for all laboratory exercises. Password-controlled access to these solutions is provided through the Altera® FPGA Academic Program. To request access, a Course Instructor must be a Member of the Altera FPGA Academic Program and can submit a request for Solutions and Source Files.
This teaching material is focused on traditional programming of embedded systems running under Linux, with emphasis on I/O methodologies. We use a DE-series board and run Linux on the dual-core ARM Cortex-A9 processor in an Altera® SoC FPGA.
The Embedded Systems material is intended to be used with one of the Teaching and Project Boards that includes an ARM processor in an Altera SoC FPGA.
Most of the software tools needed for this course, such as the embedded software development tools, are included with our Linux distribution. These Linux distributions are available via the table below.
| Supported Board | Linux Distribution Download |
|---|---|
| DE10-Standard | DE10-Standard |
| DE1-SoC | DE1-SoC |
| DE10-Nano | DE10-Nano |
For each of our supported laboratory boards (see
Teaching and Project Boards) we have developed
an accompanying ARM-based Computer System for running Linux. Each of these
Computer Systems includes an ARM processor, memory ports, basic input/output
ports (for switches, lights, etc.), and multimedia ports (for video, audio,
and the like). These Computer Systems, described below, are automatically
programmed into the available FPGA device during the Linux boot process.
| Computer System Name | Documentation |
|---|
See Embedded Linux Tutorials for instructions about downloading our Linux distribution, installing it on a DE-series board, and using this embedded software. Some of the laboratory exercises in this course rely on peripheral devices for which tutorials can be found in Hardware Components Tutorials.
These laboratory exercises cover such topics as: introduction to ARM processors and FPGA systems, introduction to embedded Linux and code development in an embedded environment, memory-mapped I/O with virtual memory in user and kernel space, kernel modules (device drivers), interrupts, and I/O devices such as buttons, switches, lights, timers, accelerometers, audio, video, A/D, USB peripherals, and developing custom hardware systems in the FPGA.
As an aid for Course Instructors, we provide complete solutions ... Password-controlled access to these solutions is provided through the Altera® FPGA Academic Program. To request access, a Course Instructor must be a Member of the Altera FPGA Academic Program and can submit a request for Solutions and Source Files.
| Lab Exercise | Downloads | Sample Solutions |
|---|
This material provides an introduction to heterogeneous computing with Altera® processors and FPGAs. We provide materials for two different design methodologies. The first approach is based on a set of tools called the Altera Acceleration Stack, which include features for the development of both hardware and software components, as well as various mechanisms for connecting these components together. The second methodology is based on the Altera® OpenCL™ compiler tools.
The Compute Acceleration materials are intended to be used with Research Boards that feature powerful, high-end Altera® FPGAs. Such boards can be accessed remotely via the Altera FPGA DevCloud®. This cloud resource also provides the software tools that are needed to support heterogeneous computing.
To perform the laboratory exercises for this course, it is necessary to have access to the Altera FPGA DevCloud®. Instructions for obtaining access to this cloud resource are provided in Compute Acceleration Tutorials.
Two types of laboratory exercises are provided, below. The first set of exercises begins with the development of a simple accelerator functional unit (AFU), which is a circuit in an FPGA that can be accessed by an Altera processor. Subsequent exercises in this set involve the development of more sophisticated AFUs that can be used to perform parts of a computation along with the processor.
The second set of laboratory exercises involve the implementation of various applications using OpenCL code, including image processing, an object classifier, and a neural network.
As an aid for Course Instructors, we provide complete solutions ... Password-controlled access to these solutions is provided through the Altera® FPGA Academic Program. To request access, a Course Instructor must be a Member of the Altera FPGA Academic Program and can submit a request for Solutions and Source Files.
| Lab Exercise | Downloads |
|---|
| Lab Exercise | Downloads |
|---|